//============================================================================
//Copyright © 2012, open source hardware engineering
// 
//This application is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public
//License as published by the Free Software Foundation; either
//version 3 of the License, or (at your option) any later version.
//
//This application is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR When PARTICULAR PURPOSE. See the GNU
//Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public
//License along with this library; if not, see <http://www.gnu.org/licenses/>
//
//=============================================================================

#ifndef AD7730.h
#define AD7730.h

#define DEFAULT_RST_PIN		2
#define DEFAULT_STBY_PIN	4
#define DEFAULT_POL_PIN		3
#define DEFAULT_RDY_PIN		5

#define DEFAULT_SS_PIN		10

#define VCC_ADC_CH			0

#define COMMS_REG			0x0		/* 8 bits, write only */
#define STAT_REG			0x0		/* 8 bits, read only */
#define DATA_REG			0x1		/* 16 or 24 bits, read only */
#define MODE_REG			0x2		/* 16 bits, R/W */
#define FILTER_REG			0x3		/* 24 bits, R/W */
#define DAC_REG				0x4		/* 8 bits, R/W */
#define OFFSET_REG			0x5		/* 24 bits, R/W */
#define GAIN_REG			0x6		/* 24 bits, R/W */
#define TEST_REG			0x7		/* 24 bits, DO NOT USE */

// Communications register bits (8 bits wide)

#define COMMS_WRITE			0x00
#define COMMS_READ			0x10
#define COMMS_START_READ	0x20		/* start continuous read operation */
#define COMMS_STOP_READ		0x30		/* stop continuous read operation */

#define COMMS_N_WEN			0x80		/* this bit is never used and s/b zero at all times */

// Status register bits (8 bits wide)

#define STAT_N_RDY			0x80
#define STAT_N_STEADY		0x40
#define STAT_STBY			0x20
#define STAT_NO_REF			0x10
#define STAT_MS3			0x08
#define STAT_MS2			0x04
#define STAT_MS1			0x02
#define STAT_MS0			0x01

// Mode register bits (16 bits wide)

#define MODEH_MODE_MASK		0xE0
#define MODEH_UNIPOLAR		0x10
#define MODEH_DEN			0x08
#define MODEH_DOUT_1		0x04
#define MODEH_DOUT_0		0x02
#define MODEH_WORD_LEN_24	0x01
#define MODEL_HIGH_REF		0x80
#define MODEL_RANGE_MASK	0x30
#define MODEL_CLK_DISABLE	0x08
#define MODEL_BURNOUT_ENA	0x04
#define MODEL_CH_MASK		0x03

// Mode bit values

#define M_IDLE				0x00
#define M_CONTINUOUS		0x20
#define M_SINGLE			0x40
#define M_STBY				0x60
#define M_INT_ZERO_CAL		0x80
#define M_INT_FS_CAL		0xA0
#define M_SYS_ZERO_CAL		0xC0
#define M_SYS_FS_CAL		0xE0


// Channel bit values

#define CH_0				0x00
#define CH_1				0x01
#define CH_SHORT			0x02
#define CH_MINUS			0x03


// Filter register bits (24-bits wide)
// split into 3 bytes, H/M/L

#define FILTH_SINC_MASK		0xFF	
#define FILTM_SINC_MASK		0xF0
#define FILTM_SKIP_FIR		0x02	/* causes FIR filter to be bypassed */
#define FILTM_FAST_STEP		0x01	/* enables FAST-Step mode (see data sheet) */
#define FILTL_AC_INPUT		0x20	/* true if input to AD7730 is chopped */
#define FILTL_CHOP_ENA		0x10	/* enables input chopping (see data sheet) */
#define FILTL_DELAY_MASK	0x0F	/* s/b zero for internal chopping (see data sheet) */

//
// DAC register bits (8 bits wide); the value is in sign/magnitude format
// The DAC resolution is VREF/2000 per bit. With a 2.500V reference,
// each DAC bit is worth 1.25mV
//
#define DAC_MASK		0x3F		/* this is a 6-bit DAC */
#define DAC_SIGN		0x20		/* the sign bit */
#define DAC_MAG			0x1F		/* unsigned magnitude bits */


#endif
